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DATA SHEET
PD780306, 780308
8-BIT SINGLE-CHIP MICROCONTROLLER
MOS INTEGRATED CIRCUIT
DESCRIPTION
PD780306 and 780308 are products in the PD780308 subseries within the 78K/0 series, which incorporates LCD
controller/driver, 8-bit resolution A/D converter, timer, serial interface, interrupt functions and many other peripheral hardwares. A one-time PROM product capable of operating in the same power supply voltage range as of the mask ROM product, EPROM product, PD78P0308, and other development tools are available. For the details of functional description, refer to the following user's manual.
PD780308, 780308Y Subseries User's Manual
78K/0 Series User's Manual (Instruction)
: U11377E : U12326E
FEATURES
* Large on-chip ROM & RAM
Item Product Name PD780306 PD780308 Program Memory (ROM) 48K bytes 60K bytes Data Memory Internal Extended RAM 1024 bytes
Internal High-Speed RAM 1024 bytes
LCD Display RAM 40 x 4 bits
* Minimum instruction execution time can be varied from high speed (0.4 s) to ultra-low speed (122 s) * I/O ports: 57 (including segment signal output alternate-function pins) * LCD controller/driver Supply voltage VDD = 2.0 to 5.5 V (Operable in any mode) * 8-bit resolution A /D converter : 8 channels * Serial interface : 3 channels * Timer: 5 channels * Supply voltage : VDD = 2.0 to 5.5 V
APPLICATIONS
Celullar phones, compact disk players, cameras, meters, etc.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U11105EJ3V1DS00 (3rd edition) Date Published June 2001 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1996
PD780306, 780308
ORDERING INFORMATION
Part Number Package 100-pin plastic LQFP (Fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic LQFP (Fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm)
PD780306GC-xxx-8EU PD780306GF-xxx-3BA PD780308GC-xxx-8EU PD780308GF-xxx-3BA
Remark
xxx indicates ROM code suffix.
2
Data Sheet U11105EJ3V1DS
PD780306, 780308
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD78014H PD78018F PD78083
Inverter control
EMI-noise reduced version of the PD78078
PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y
PD78054 with timer and enhanced external interface
ROMless version of the PD78078 PD78078Y with enhanced serial I/O and limited function
PD78054 with enhanced serial I/O
EMI-noise reduced version of the PD78054
PD78018F with UART and D/A converter, and enhanced I/O PD780024A with expanded RAM PD780034A with timer and enhanced serial I/O PD780078Y PD780034AY PD780024A with enhanced A/D converter PD780024AY PD78018F with enhanced serial I/O EMI-noise reduced version of the PD78018F PD78018FY
Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
PD780988
VFD drive
On-chip inverter control circuit and UART. EMI-noise reduced.
100-pin 78K/0 Series 80-pin 80-pin 80-pin
PD780208 PD780232 PD78044H PD78044F
LCD drive
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open-drain I/O. Display output total: 34
Basic subseries for driving VFD. Display output total: 34
120-pin 120-pin 120-pin 100-pin 100-pin 100-pin
PD780338 PD780328 PD780318 PD780308 PD78064B PD78064
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max. PD780308 with enhanced display function and timer. Segment signal output: 32 pins max. PD780308 with enhanced display function and timer. Segment signal output: 24 pins max. PD780308Y PD78064Y PD78064 with enhanced SIO, and expanded ROM and RAM EMI-noise reduced version of the PD78064
Basic subseries for driving LCDs, on-chip UART
Bus interface supported 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin
PD780948 PD78098B PD780702Y PD780703Y PD780833Y
PD780816
Meter control
On-chip DCAN controller
PD78054 with IEBusTM controller.
On-chip IEBus controller On-chip DCAN controller On-chip controller compliant with J1850 (Class 2) Specialized for DCAN controller function
100-pin 80-pin 80-pin
PD780958 PD780852 PD780824
For industrial meter control On-chip automobile meter controller/driver For automobile meter driver. On-chip DCAN controller
Remark
VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same.
Data Sheet U11105EJ3V1DS
3
PD780306, 780308
The major functional differences among the subseries are shown below.
Function Subseries Name Control ROM Capacity Timer 8-bit 16-bit Watch WDT 1 ch 1 ch 1 ch 8-Bit 10-Bit 8-Bit A/D 8 ch A/D - D/A 2 ch 3 ch (UART: 1 ch) 88 Serial Interface I/O VDD External MIN. Value Expansion 1.8 V Yes
PD78075B 32 K to 40 K 4 ch PD78078 PD78070A
48 K to 60 K -
61 3 ch (time-division UART: 1 ch) 3 ch (UART: 1 ch) 68 69
2.7 V 1.8 V 2.7 V 2.0 V
PD780058 24 K to 60 K 2 ch PD78058F 48 K to 60 K PD78054
16 K to 60 K - 2 ch 1 ch 8 ch - - 8 ch
PD780065 40 K to 48 K PD780078 48 K to 60 K
PD780034A 8 K to 32 K PD780024A
4 ch (UART: 1 ch) 3 ch (UART: 2 ch) 3 ch (UART: 1 ch)
60 52 51
2.7 V 1.8 V
PD78014H PD78018F 8 K to 60 K PD78083
Inverter control VFD drive 8 K to 16 K - - - 1 ch - 8 ch -
2 ch
53
1 ch (UART: 1 ch) 3 ch (UART: 2 ch)
33 47 4.0 V
- Yes
PD780988 16 K to 60 K 3 ch Note PD780208 32 K to 60 K 2 ch PD780232 16 K to 24 K 3 ch PD78044H 32 K to 48 K 2 ch PD78044F 16 K to 40 K
1 ch - 1 ch
1 ch - 1 ch
1 ch
8 ch 4 ch 8 ch
-
-
2 ch
74 40
2.7 V 4.5 V 2.7 V
-
1 ch 2 ch
68
LCD drive
PD780338 48 K to 60 K 3 ch PD780328 PD780318 PD780308 48 K to 60 K 2 ch PD78064B 32 K PD78064
16 K to 32 K 2 ch
2 ch
1 ch
1 ch
-
10 ch 1 ch 2 ch (UART: 1 ch)
54 62 70
1.8 V
-
1 ch
8 ch
-
-
3 ch (time-division UART: 1 ch) 2 ch (UART: 1 ch)
57
2.0 V
Bus interface
PD780948 60 K PD78098B 40 K to 60 K
2 ch 1 ch 2 ch 2 ch
1 ch
1 ch
8 ch
-
- 2 ch
3 ch (UART: 1 ch)
79 69
4.0 V 2.7 V 4.0 V 2.2 V
Yes -
supported PD780816 32 K to 60 K Meter control Dash board control
12 ch - 1 ch - -
- -
2 ch (UART: 1 ch) 2 ch (UART: 1 ch)
46 69
PD780958 48 K to 60 K 4 ch PD780852 32 K to 40 K 3 ch PD780824 32 K to 60 K
-
1 ch
1 ch
1 ch
5 ch
-
-
3 ch (UART: 1 ch) 2 ch (UART: 1 ch)
56 59
4.0 V
-
Note
16-bit timer: 2 channels 10-bit timer: 1 channel
4
Data Sheet U11105EJ3V1DS
PD780306, 780308
OVERVIEW OF FUNCTION
Product Name Item Internal memory ROM High-speed RAM Extended RAM LCD display RAM
PD780306
48K bytes
PD780308
General-purpose registers Minimum instruction execution time When main system clock selected When subsystem clock selected
60K bytes 1024 bytes 1024 bytes 40 x 4 bits 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip minimum instruction execution time cycle modification function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz operation) 122 s (at 32.768 kHz operation) * * * * 16-bit operation Multiplication/division (8 bits x 8 bits,16 bits / 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD correction, etc. Total : 57 * CMOS input : 02 * CMOS I/O : 55 8-bit resolution x 8 channels Segment signal output : Maximum 40 Common signal output : Maximum 4 Bias : 1/2 or 1/3 switchable 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel 3-wire serial I/O/UART mode selectable : 1 channel 3-wire serial I/O mode : 1 channel 16-bit timer/event counter : 1 channel 8-bit timer/event counter : 2 channels Watch timer : 1 channel Watchdog timer : 1 channel
Instruction set
I/O ports (including segment signal output pins) A/D converter LCD controller/driver * * * * * * * * * * *
Serial interface
Timer
Timer output
3 (14-bit PWM output capability : 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (at main system clock: 5.0 MHz operation) 32.768 kHz (at subsystem clock: 32.768 kHz operation) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 5.0 MHz operation) Maskable Non-maskable Software Internal : 13, external : Internal : 1 1 Internal : 1, external: 1 VDD = 2.0 to 5.5 V * 100-pin plastic LQFP (Fine pitch) (14 x 14 mm) * 100-pin plastic QFP (14 x 20 mm) 6
Clock output
Buzzer output Vectored interrupt sources Test input Supply voltage Package
Data Sheet U11105EJ3V1DS
5
PD780306, 780308
CONTENTS
1. 2. 3.
PIN CONFIGURATION (TOP VIEW) .......................................................................................................... 7 BLOCK DIAGRAM .................................................................................................................................... 10 PIN FUNCTIONS ....................................................................................................................................... 11
3.1 3.2 3.3 PORT PINS ......................................................................................................................................................... 11 NON-PORT PINS ................................................................................................................................................ 13 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ............................................ 14
4. 5.
MEMORY SPACE ...................................................................................................................................... 18 PERIPHERAL HARDWARE FUNCTION FEATURE .............................................................................. 19
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 PORT ................................................................................................................................................................... 19 CLOCK GENERATOR ....................................................................................................................................... 20 TIMER/EVENT COUNTER ................................................................................................................................. 20 CLOCK OUTPUT CONTROL CIRCUIT ............................................................................................................ 23 BUZZER OUTPUT CONTROL CIRCUIT .......................................................................................................... 23 A/D CONVERTER .............................................................................................................................................. 24 SERIAL INTERFACE ......................................................................................................................................... 25 LCD CONTROLLER/DRIVER ............................................................................................................................ 27
6.
INTERRUPT FUNCTIONS AND TEST FUNCTIONS .............................................................................. 28
6.1 6.2 INTERRUPT FUNCTIONS ................................................................................................................................. 28 TEST FUNCTIONS ............................................................................................................................................. 32
7. 8. 9.
STANDBY FUNCTION .............................................................................................................................. 33 RESET FUNCTION .................................................................................................................................... 33 INSTRUCTION SET ................................................................................................................................... 34
10. ELECTRICAL SPECIFICATIONS ............................................................................................................. 37 11. CHARACTERISTIC CURVES (REFERENCE VALUE) ........................................................................... 58 12. PACKAGE DRAWINGS ............................................................................................................................ 60 13. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 62 APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 63 APPENDIX B. RELATED DOCUMENTS ........................................................................................................ 66
6
Data Sheet U11105EJ3V1DS
PD780306, 780308
1. PIN CONFIGURATION (TOP VIEW)
* 100-pin plastic LQFP (Fine pitch) (14 x 14 mm)
PD780306GC-xxx-8EU, 780308GC-xxx-8EU
P72/SCK2/ASCK
P113/TxD P112/SCK3 P111/SO3 P110/SI3 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET
P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 VDD0 AVREF P100 P101 VSS1 P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 COM0 COM1 COM2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 74 2 73 3 72 4
P71/SO2/TXD
AVSS P117 P116 P115 P114/RxD
P10/ANI0
XT1/P07 VDD1
XT2
X1 X2 IC
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
P70/SI2/RXD P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 S20 S19
54 22 53 23 52 24 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
COM3 BIAS VLC0
S6 S7 S8 S9 S10 S11 S12
S13 S14 S15 S16 S17
VLC1 VLC2 VSS0
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS0 or VSS1. 2. Connect the AVSS pin to VSS0. Remark When using in applications where noise from inside the microcontroller has to be reduced, it is recommended that countermeasures against the noise are taken, such as supplying power separately to VDD0 and VDD1, and connecting VDD0 and VDD1 to ground lines separately.
S18
S0 S1 S2
S3 S4 S5
Data Sheet U11105EJ3V1DS
7
PD780306, 780308
* 100-pin plastic QFP (14 x 20 mm)
PD780306GF-xxx-3BA, 780308GF-xxx-3BA
P25/SI0/SB0
P80/S39 P81/S38 P82/S37 P83/S36 P84/S35
P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24
S23
P26/SO0/SB1 P27/SCK0 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK IC X2 X1 VDD1 XT1/P07 XT2 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P110/SI3 P111/SO3 P112/SCK3 P113/TxD P114/RxD P115 P116 P117 AVSS P10/ANI0 P11/ANI1 P12/ANI2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 79 2 78 3 77 4
S22 S21
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 VSS0 VLC2 VLC1 VLC0 BIAS COM3 COM2 COM1 COM0
53 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P13/ANI3 P14/ANI4 P15/ANI5
P16/ANI6 P17/ANI7 VDD0
P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ
AVREF P100 P101
VSS1 P102 P103
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS0 or VSS1. 2. Connect the AVSS pin to VSS0. Remark When using in applications where noise from inside the microcontroller has to be reduced, it is recommended that countermeasures against the noise are taken, such as supplying power separately to VDD0 and VDD1, and connecting VDD0 and VDD1 to ground lines separately.
8
Data Sheet U11105EJ3V1DS
P37
PD780306, 780308
ANI0-ANI7 ASCK AVREF AVSS BIAS BUZ COM0-COM3 IC INTP0-INTP5 P00-P05, P07 P10-P17 P25-P27 P30-P37 P70-P72 P80-P87 P90-P97 P100-P103 P110-P117 : Analog Input : Asynchronous Serial Clock : Analog Reference Voltage : Analog Ground : LCD Power Supply Bias Control : Buzzer Clock : Common Output : Internally Connected : Interrupt from Peripherals : Port0 : Port1 : Port2 : Port3 : Port7 : Port8 : Port9 : Port10 : Port11 PCL RESET RxD S0-S39 SB0, SB1 SI0, SI2, SI3 SO0, SO2, SO3 TI00, TI01, TI1, TI2 TO0-TO2 TxD VDD0, VDD1 VLC0-VLC2 VSS0, VSS1 X1, X2 XT1, XT2 : Programmable Clock : Reset : Receive Data : Segment Output : Serial Bus : Serial Input : Serial Output : Timer Input : Timer Output : Transmit Data : Power Supply : LCD Power Supply : Ground : Crystal (Main System Clock) : Crystal (Subsystem Clock)
SCK0, SCK2, SCK3 : Serial Clock
Data Sheet U11105EJ3V1DS
9
PD780306, 780308
2. BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit timer/ event counter
P00 PORT 0 P01-P05 P07
8-bit timer/ event counter 1 8-bit timer/ event counter 2
PORT 1
P10-P17
PORT 2
P25-P27
Watchdog timer
PORT 3
P30-P37
Watch timer SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI2/RxD/P70 SO2/TxD/P71 RxD/P114 TxD/P113 SCK2/ASCK/P72 SI3/P110 SO3/P111 SCK3/P112 ANI0/P10ANI7/P17 AVSS AVREF INTP0/P00INTP5/P05 BUZ/P36 A/D converter RAM Serial interface 3 Serial interface 0 78K/0 CPU core Serial interface 2 ROM
PORT 7
P70-P72
PORT 8
P80-P87
PORT 9
P90-P97
PORT 10
P100-P103
PORT 11
P110-P117
S0-S23 S24/P97S31/P90 S32/P87S39/P80 COM0-COM3 VLC0-VLC2
LCD controller/ driver
Interrupt control Buzzer output Clock output control System control
BIAS fLCD RESET X1 X2 XT1/P07 XT2
PCL/P35
VDD0, VDD1 VSS0, VSS1
IC
Remark The internal ROM capacity varies depending on the product.
10
Data Sheet U11105EJ3V1DS
PD780306, 780308
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
Alternate Function INTP0/TI00 INTP1/TI01 Input/ output Port 0 7-bit Input/output port. Input/output can be specified bit-wise. When used as an input port, internal pull-up resistor can be used by software. INTP2 Input INTP3 INTP4 INTP5 Input Input only Port 1 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, internal pull-up resistor can be used by software.Note 2 Port 2 3-bit input/output port. Input/output can be specified bit-wise. When used as an input port, internal pull-up resistor can be used by software. Input XT1
Pin Name P00 P01 P02 P03 P04 P05 P07
Note 1
I/O Input
Function Input only
On Reset Input
P10-P17
Input/ output
Input
ANI0-ANI7
P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P70 P71 P72 Input/ output Input/ output Input/ output
SI0/SB0 Input SO0/SB1 SCK0 TO0 TO1
Port 3 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, internal pull-up resistor can be used by software.
TO2 Input TI1 TI2 PCL BUZ --
Port 7 3-bit input/output port. Input/output can be specified bit-wise. When used as an input port, internal pull-up resistor can be used by software.
SI2/RxD SO2/TxD Input SCK2/ASCK
Notes 1. 2.
When using the P07/XT1 pins as an input port, set (1) bit 6 (FRC) of the processor clock control register (PCC) (the on-chip feedback resistor of the subsystem clock oscillator should not be used). When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, port 1 is set to input mode. However, internal pull-up resistor is not automatically used.
Data Sheet U11105EJ3V1DS
11
PD780306, 780308
3.1 NON-PORT PINS (2/2)
Alternate Function
Pin Name
I/O
Function Port 8 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, internal pull-up resistor can be used by software. Input/output port/segment signal output function can be specified in 2-bit unit by the LCD display control register (LCDC). Port 9 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, internal pull-up resistor can be used by software. Input/output port/segment signal output function can be specified in 2-bit unit by the LCD display control register (LCDC). Port 10 4-bit input/output port Input/output can be specified bit-wise. When used as an input port, internal pull-up resistor can be used by software. LED direct drive capability.
On Reset
P80-P87
Input/ output
Input
S39-S32
P90-P97
Input/ output
Input
S31-S24
P100-P103
Input/ output
Input
--
P110 P111 P112 P113 P114 P115-P117 Input/ output Port 11 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, internal pull-up resistor can be used by software. Falling edge detection capability.
SI3 SO3 Input SCK3 TxD RxD --
12
Data Sheet U11105EJ3V1DS
PD780306, 780308
3.2 NON-PORT PINS (1/2)
Alternate Function P00/TI00 P01/TI01 Input External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. Input P02 P03 P04 P05 P25/SB0 Input Serial interface serial data input. Input P70/RxD P110 P26/SB1 Output Serial interface serial data output. Input P71/TxD P111 Input/ output Serial interface serial data input/output. P25/SI0 Input P26/SO0 P27 Input/ output Input Output Input Serial interface serial clock input/output. Input P72/ASCK P112 Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input. External count clock input to 16-bit timer (TM0). Capture trigger signal input to capture register (CR00). Input External count clock input to 8-bit timer (TM1). External count clock input to 8-bit timer (TM2). 16-bit timer (TM0) output (shared with 14-bit PWM output). Output 8-bit timer (TM1) output. 8-bit timer (TM2) output. Output Output Clock output (for main system clock, subsystem clock trimming). Buzzer output. Input Input Output Output LCD controller/driver segment signal output. Input Output -- -- Input Input Input Input Input P70/SI2, P114 P71/SO2, P113 P72/SCK2 P00/INTP0 P01/INTP1 P33 P34 P30 P31 P32 P35 P36 -- P97-P90 P87-P80 Output -- -- LCD controller/driver common signal output. LCD drive voltage. Split resistors can be incorporated by mask option. LCD drive power supply. -- -- --
Pin Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SI0 SI2 SI3 SO0 SO2 SO3 SB0 SB1 SCK0 SCK2 SCK3 RxD TxD ASCK TI00 TI01 TI1 TI2 TO0 TO1 TO2 PCL BUZ S0-S23 S24-S31 S32-S39 COM0-COM3 VLC0-VLC2 BIAS
I/O
Function
On Reset
Data Sheet U11105EJ3V1DS
13
PD780306, 780308
3.2 NON-PORT PINS (2/2)
I/O Input Input A/D converter analog input. Reference voltage input of A/D converter (shared with analog power -- supply). AVSS -- Ground potential of A/D converter. -- Set the same potential as VSS0. RESET X1 X2 XT1 XT2 VDD0 VSS0 VDD1 VSS1 IC Input Input Main system clock oscillation crystal connection. -- Input Subsystem clock oscillation crystal connection. -- -- -- -- -- -- Positive power supply for port block. Ground potential for port block. Positive power supply (except port and analog block). Ground potential (except port and analog block). Internally connected. Connect directly to VSS0 or VSS1 pin. -- -- -- -- -- -- -- -- -- -- -- -- -- Input -- P07 System reset input. -- -- -- -- -- -- Function On Reset Input Alternate Function P10-P17
Pin Name ANI0-ANI7 AVREF
3.3
PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Input/Output Circuit Type of Each Pin (1/2)
Pin Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 P10/ANI0-P17/ANI7 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 Input/output P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 8-C 5-H Independently connect to VDD0 or VSS0 through resistor. 10-B 16 11-B Input Connect to VDD0. 8-C Input/output Independently connect to VSS0 through resistor. Input/output Circuit Type 2 I/O Input Recommended Connection When Not Used Connect to VSS0.
14
Data Sheet U11105EJ3V1DS
PD780306, 780308
Table 3-1. Input/Output Circuit Type of Each Pin (2/2)
Input/output Circuit Type
Pin Name P35/PCL P36/BUZ P37 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P80/S39 to P87/S32
I/O
Recommended Connection When Not Used
5-H
8-C 5-H 8-C 17-C Independently connect to VDD0 or VSS0 through resistor.
P90/S31 to P97/S24 P100 to P103 P110/SI3 P111/SO3 P112/SCK3 P113/TxD P114/RxD P115 to P117 S0 to S23 COM0 to C0M3 VLC0 to VLC2 -- BIAS RESET XT2 AVREF 2 16 17-B 5-H 8-C
Input/output
Independently connect to VDD0 through resistor.
Output 18-A Leave unconnected. -- Input Leave unconnected. Connect to VSS0. -- AVSS IC -- Connect to VSS0. Connect directly to VSS0 or VSS1. --
Data Sheet U11105EJ3V1DS
15
PD780306, 780308
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 2 Type 10-B
VDD0 Pull-up enable VDD0
IN
P-ch
Data
P-ch IN/OUT
Open-drain output disable
Schmitt-triggered input with hysteresis characteristic
N-ch VSS0
Type 5-H VDD0 Pull-up enable VDD0 Data P-ch IN/OUT Output disable N-ch VSS0
Type 11-B
VDD0 Pull-up enable Data
P-ch
P-ch VDD0 P-ch IN/OUT
Output disable Comparator
+ -
N-ch P-ch VSS0
Input enable
VSS0 N-ch VREF (Threshold voltage) Input enable
Type 8-C
Type 16
VDD0
Feedback cut-off
Pull-up enable VDD0 Data P-ch
P-ch
P-ch
IN/OUT Output disable N-ch VSS0
XT1
XT2
16
Data Sheet U11105EJ3V1DS
PD780306, 780308
Figure 3-1. Pin Input/Output Circuits (2/2)
Type 17-B Type 17-C
VLC0 P-ch VLC1 N-ch P-ch SEG data P-ch VLC2 N-ch N-ch OUT
VDD0
Pull-up enable VDD0 Data P-ch
P-ch
IN/OUT Output disable VSS0 Input enable VLC0 P-ch VLC1 N-ch N-ch
VSS1
Type 18-A
VLC0 P-ch VLC1 N-ch N-ch P-ch
P-ch SEG data P-ch VLC2
P-ch OUT
N-ch
N-ch
COM data P-ch VLC2 N-ch
N-ch
VSS1
VSS1
Data Sheet U11105EJ3V1DS
17
PD780306, 780308
4. MEMORY SPACE
The memory map of PD780306 and 780308 is shown in Figure 4-1.
Figure 4-1. Memory Map
FFFFH
Special function register (SFR) 256 x 8 bits
FF00H FEFFH General-purpose registers FEE0H FEDFH 32 x 8 bits
Internal high-speed RAM 1024 x 8 bits
FB00H FAFFH
Data memory space
nnnnH Reserved LCD display RAM 40 x 4 bits 1000H 0FFFH CALLF entry area Reserved 0800H 07FFH Program area 0080H 007FH Reserved CALLT table area 0040H 003FH Vector table area Program area
FA80H FA7FH FA58H FA57H F800H F7FFH Internal extended RAM 1024 x 8 bits F400H F3FFH nnnnH+1 nnnnH
Program memory space
Internal ROMNote
0000H
0000H
Note
The capacity of Internal ROM differs according to product. (refer to the following table.)
Product Name
Last Address of Internal ROM nnnnH BFFFH EFFFH
PD780306 PD780308
18
Data Sheet U11105EJ3V1DS
PD780306, 780308
5. PERIPHERAL HARDWARE FUNCTION FEATURE
5.1 PORT
There are two kinds of I/O port. * CMOS input (P00, P07) * CMOS input/output (P01 to P05, Port 1 to 3, 7 to 11) Total :2 : 55 : 57
Table 5-1. Functions of Ports
Name
Pin Name P00, P07 Dedicated input port
Function
Port 0
P01 to P05 P10 to P17 P25 to P27 P30 to P37 P70 to P72
Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used by software. Input/output port. Input/output specifialbe bit-wise. When used as input port, on-chip pull-up resistor can be used by software. Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used by software. Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used by software. Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used by software. Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used by software. Input/output port/segment signal output function specifiable in 2-bit units by LCD display control register (LCDC). Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used by software. Input/output port/segment signal output function specifiable in 2-bit units by LCD display control register (LCDC). Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used by software. Direct LED drive capability. Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection.
Port 1 Port 2 Port 3 Port 7
Port 8
P80 to P87
Port 9
P90 to P97
Port 10
P100 to P103
Port 11
P110 to P117
Data Sheet U11105EJ3V1DS
19
PD780306, 780308
5.2 CLOCK GENERATOR
There are two kinds of clocks, main system clock and subsystem clock. The minimum instruction execution time can also be changed. * 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (main system clock: in 5.0 MHz operation) * 122 s (subsystem clock: in 32.768 kHz operation) Figure 5-1. Clock Generator Block Diagram
XT1/P07 XT2
Subsystem clock oscillator
fXT
Watch timer Clock output function Prescaler
X1 X2
Main system clock oscillator
fX Frequency divider
Selector fX 2
Prescaler fXX fXX 2 fXX 22 fXX 23 1/2 fXX fXT 24 2 Standby control circuit
Clock to peripheral hardware
STOP Selector CPU clock (fCPU)
To INTP0 sampling clock
5.3
TIMER/EVENT COUNTER * 16-bit timer/event counter * 8-bit timer/event counter * Watch timer * Watchdog timer : 1 channel : 2 channels : 1 channel : 1 channel
Five timer/event counter channels are incorporated.
Table 5-2. Operation of Timer/Event Counter
16-bit Timer/ Event Counter Operating mode Interval timer External event counter Timer output PWM output Pulse width measurement Square wave output One-shot pulse output Interrupt request Test input 1 channel 1 channel 1 output 1 output 2 inputs 1 output 1 output 2 - 8-bit Timer/ Event Counter 2 channels 2 channels 2 outputs - - 2 outputs - 2 -
Watch Timer 1 channel - - - - - - 1 1 input
Watchdog Timer 1 channel - - - - - - 1 -
Function
20
Data Sheet U11105EJ3V1DS
PD780306, 780308
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal bus INTP1 TI01/P01/INTP1 Selector 16-bit capture/compare register (CR00) PWM pulse output control circuit
INTTM00
Match Watch Timer Output 2fXX fXX fXX/2 fXX/22 TI00/P00/INTP0 Edge detector Match Selector 16-bit timer register (TM0) Clear
Output control circuit
TO0/P30
Selector INTTM01 INTP0
16-bit capture/compare register (CR01)
Internal bus
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal bus
INTTM1 8-bit compare register (CR10)
8-bit compare register (CR20) Selector Match
Match
Output control circuit
TO2/P32
fXX/2-fXX/29 fxX/211 TI1/P33 Clear fXX/2-fXX/29 fxX/211 TI2/P34 Output control circuit Internal bus Selector Selector 8-bit timer register 1 (TM1) 8-bit timer register 2 (TM2) Clear Selector
INTTM2
Selector
TO1/P31
Data Sheet U11105EJ3V1DS
21
PD780306, 780308
Figure 5-4. Watch Timer Block Diagram
fW 214 fXX/27 fXT fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 Selec- fW tor Selector Prescaler fW 213 5-bit counter Selector INTWT
Selector
INTTM3 To 16-bit timer/event counter To LCD controller/driver
Figure 5-5. Watchdog Timer Block Diagram
fXX 23 fXX 24 fXX 25 fXX 26
Prescaler fXX 27 fXX 28 fXX 29 fXX 211 INTWDT maskable interrupt request Selector 8-bit counter Control circuit RESET INTWDT non-maskable interrupt request
22
Data Sheet U11105EJ3V1DS
PD780306, 780308
5.4 CLOCK OUTPUT CONTROL CIRCUIT * 19.5 kHz/39.1kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (main system clock: in 5.0 MHz operation) * 32.768 kHz (subsystem clock: in 32.768 kHz operation) Figure 5-6. Clock Output Control Circuit Block Diagram
fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXT
Clocks of the following frequency can be output as clock outputs.
Selector
Synchronization circuit
Output control circuit
PCL/P35
5.5
BUZZER OUTPUT CONTROL CIRCUIT * 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (main system clock : in 5.0 MHz operation) Figure 5-7. Buzzer Output Control Circuit Block Diagram
Clocks of the following frequency can be output as buzzer outputs.
fXX/29 fXX/210 fXX/2
11
Selector
Output control circuit
BUZ/P36
Data Sheet U11105EJ3V1DS
23
PD780306, 780308
5.6 A/D CONVERTER
Eight 8-bit resolution A/D converter channels are incorporated. The following two types of start-up method are available. * Hardware start * Software start Figure 5-8. A/D Converter Block Diagram
Series resistor string ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Successive approximation register (SAR) AVSS Selector Sample & hold circuit Voltage comparator Tap selector AVREF
INTP3/P03
Edge detector
Control circuit
INTAD INTP3
A/D conversion result register (ADCR)
Internal bus
24
Data Sheet U11105EJ3V1DS
PD780306, 780308
5.7 SERIAL INTERFACE * Serial interface channel 0 * Serial interface channel 2 * Serial interface channel 3 Table 5-3. Serial Interface Channel Block Diagram
Three clocked serial interface channels are incorporated.
Function 3-wire serial I/O mode SBI (serial bus interface) mode 2-wire serial I/O mode Asynchronous serial interface (UART) mode
Serial Interface Channel 0 (MSB/LSB-first switchable) (MSB-first) (MSB-first) --
Serial Interface Channel 2 (MSB/LSB-first switchable) -- -- (With dedicated baud rate generator, data I/O pin switch function)
Serial Interface Channel 3 (MSB/LSB-first switchable) -- -- --
Figure 5-9. Serial Interface Channel 0 Block Diagram
Internal bus
SI0/SB0/P25 Selector SO0/SB1/P26 Serial I/O shift register 0 (SIO0) Output latch
Selector
Bus release/command/ acknowledge detector Interrupt request signal generator
Busy/acknowledge output circuit
SCK0/P27
Serial clock counter
INTCSI0
fXX/2-fXX/28 Serial clock control circuit Selector TO2
Data Sheet U11105EJ3V1DS
25
PD780306, 780308
Figure 5-10. Serial Interface Channel 2 Block Diagram
Internal bus
Receive buffer register (RXB/SIO2)
Direction control circuit
Direction control circuit RXD/P114 Selector RXD/SI2/P70 TXD/SO2/P71 Selector TXD/P113 ASCK/SCK2/P72 Receive control circuit Receive shift register (RXS)
Transmit shift register (TXS/SIO2)
Transmit control circuit
INTST
INTSER INTSR/INTCSI2 SCK output control circuit
Baud rate generator
fXX-fXX/210
Figure 5-11. Serial Interface Channel 3 Block Diagram
Internal bus
SI3/P110
Serial I/O shift register 3 (SIO3)
SO3/P111 Interrupt request signal generator
SCK3/P112
Serial clock counter
INTCSI3
fXX/2-fXX/28 Serial clock control circuit Selector
26
Data Sheet U11105EJ3V1DS
PD780306, 780308
5.8 LCD CONTROLLER/DRIVER * Selection of 5 types of display mode * 16 of the segment signal of outputs can be switched to input/output ports in units of 2. (P80/S39 to P87/S32, P90/S31 to P97/S24) Table 5-4. Display Mode Types and Maximum Number of Display Pixels
Bias Method ---- 1/2 1/3 Time Division Static 2 3 3 4 Common Signal Used COM0 (COM1 to COM3) COM0, COM1 COM0 to COM2 COM0 to COM2 COM0 to COM3 Maximum Number of Display Pixels 40 (40 segments x 1 common) 80 (40 segments x 2 commons) 120 (40 segments x 3 commons) 160 (40 segments x 4 commons)
An LCD controller/driver with the following functions is incorporated.
Figure 5-12. LCD Controller/Driver Block Diagram
Internal bus
Prescaler Display data memory Timing controller Segment data selector Port output data LCD drive voltage generator Segment driver Common driver LCDCL Selector LCD drive mode switch circuit fW 29 fW 28 fW 27
fW 26
S0
S23 S24/P97
S39/P80
COM0 COM1 COM2 COM3
VLC2
VLC1
VLC0
BIAS
Data Sheet U11105EJ3V1DS
27
PD780306, 780308
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 INTERRUPT FUNCTIONS * Non-maskable * Maskable * Software :1 : 19 :1
There are twenty-one of interrupt sources of three different kinds, as shown below.
28
Data Sheet U11105EJ3V1DS
PD780306, 780308
Table 6-1. Interrupt Source List
Interrupt Type Nonmaskable
Default Priority Note 1
Interrupt Source Name INTWDT INTWDT INTP0 INTP1 INTP2 Pin input edge detection INTP3 INTP4 INTP5 INTCSI0 INTSER INTSR Serial interface channel 0 transfer termination Serial interface channel 2 UART reception error generation Serial interface channel 2 UART reception termination Serial interface channel 2 3-wire transfer termination Serial interface channel 2 UART transmission termination Reference time interval signal from watch timer Trigger Watchdog timer overflow (with watchdog timer mode 1 selected)
Internal/ External
Vector Table Address
Basic Configuration Type Note 2 (A)
---- 0 1 2 3 4 5 6 7 8
Internal Watchdog timer overflow (with interval timer mode selected)
0004H (B) 0006H 0008H 000AH (C)
External
000CH 000EH 0010H 0014H 0018H
(D)
Maskable
9 INTCSI2 10 11 12 13 14 15 16 17 INTST INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD INTCSI3 BRK
001AH
001CH 001EH Internal (B) 0020H 0022H 0024H 0026H 0028H 002AH ---- 003EH (E)
16-bit timer register and capture/compare register (CR00) match signal generation 16-bit timer register and capture/compare register (CR01) match signal generation 8-bit timer/event counter 1 match signal generation 8-bit timer/event counter 2 match signal generation A/D converter conversion termination Serial interface channel 3 transfer termination BRK instruction execution
Software
----
Notes 1. 2.
Default priority is a priority order when more than one maskable interrupt request is generated simultaneously. 0 is the highest and 17 the lowest. Basic configuration types (A) to (E) correspond to those shown on the next page.
Data Sheet U11105EJ3V1DS
29
PD780306, 780308
Figure 6-1. Basic Configuration of Interrupt Functions (1/2) (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Priority control circuit
Vector table address generator Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority control circuit
Vector table address generator Standby release signal
(C) External maskable interrupt (INTP0)
Internal bus
Sampling clock select register (SCS)
External interrupt mode register (INTM0)
MK
IE
PR
ISP
Interrupt request
Sampling clock
Edge detector
IF
Priority control circuit
Vector table address generator Standby release signal
30
Data Sheet U11105EJ3V1DS
PD780306, 780308
Figure 6-1. Basic Configuration of Interrupt Functions (2/2) (D) External maskable interrupt (except INTP0)
Internal bus
External interrupt mode register (INTM0, INTM1)
MK
IE
PR
ISP
Interrupt request
Edge detector
IF
Priority control circuit
Vector table address generator Standby release signal
(E) Software interrupt
Internal bus
Interrupt request
Priority control circuit
Vector table address generator
IF IE
: Interrupt request flag : Interrupt enable flag
ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specification flag
Data Sheet U11105EJ3V1DS
31
PD780306, 780308
6.2 TEST FUNCTIONS
There are two test functions as shown in Table 6-2. Table 6-2. Test Input Source List
Test Input Source Name INTWT INTPT11 Trigger Watch timer overflow Port 11 falling edge detection Internal/External Internal External
Figure 6-2. Basic Configuration of Test Function
Internal bus
MK
Test input signal
IF
Standby release signal
IF
: Test input flag
MK : Test mask flag
32
Data Sheet U11105EJ3V1DS
PD780306, 780308
7. STANDBY FUNCTION
The standby function is a function to reduce the current consumption and there are the following two kinds of standby functions. * HALT mode : Halts CPU operating clock and can reduce average current consumption by the intermittent operation along with the normal operation. * STOP mode : Halts main system clock oscillation. Halts all operations with the main system clock and sets ultralow current consumption state with subsystem clock only. Figure 7-1. Standby Function
CSS=1 Main system clock operation CSS=0 STOP instruction Interrupt request STOP mode Main system clock oscillation halted Interrupt request HALT instruction Interrupt request HALT instruction Subsystem clock operation
Note
(
)
(
HALT mode Clock supply to CPU halted, oscillation maintained
)
(
HALT modeNote Clock supply to CPU halted, oscillation maintained
)
Note
Halting the main system clock enables the current consumption to be reduced. When the CPU is operated by the subsystem clock, the main system clock should be halted by setting the bit 7 (MCC) of the processor clock control register (PCC). The STOP instruction is not available.
Caution When the main system clock is stopped and the system is operated by the subsystem clock, the main system clock should be returned to after securing the oscillation stabilization time by a program.
8. RESET FUNCTION
There are the following two kinds of resetting methods. * External reset by RESET pin. * Internal reset by watchdog timer hung-up time detection.
Data Sheet U11105EJ3V1DS
33
PD780306, 780308
9. INSTRUCTION SET
(1) 8-bit instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand 1st Operand A #byte ADD ADDC SUB SUBC AND OR XOR CMP A
[HL+byte] [HL+B] $addr16 [HL+C]
rNote MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
sfr MOV XCH
saddr MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
!addr16 MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
PSW MOV
[DE] MOV XCH
[HL] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
1 ROR ROL RORC ROLC
None
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
r
MOV
MOV ADD ADDC SUB SUBC AND OR XOR CMP DBNZ MOV MOV
INC DEC
B, C sfr saddr
MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV
DBNZ
INC DEC
!addr16 PSW [DE] [HL] [HL+byte] [HL+B] [HL+C] X C
MOV MOV MOV MOV MOV
PUSH POP ROR4 ROL4
MULU DIVUW
Note Except r = A
34
Data Sheet U11105EJ3V1DS
PD780306, 780308
(2) 16-bit instruction MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand #word 1st Operand AX ADDW SUBW CMPW MOVW MOVW MOVW MOVW MOVW XCHW MOVWNote MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW AX
rpNote
sfrp
saddrp
!addr16
SP
None
rp sfrp saddrp !addr16 SP
INCW, DECW PUSH, POP
Note Only when rp = BC, DE, HL (3) Bit manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand A.bit 1st Operand A.bit MOV1 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 sfr.bit saddr.bit PSW.bits [HL].bit CY $addr16 None
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
Data Sheet U11105EJ3V1DS
35
PD780306, 780308
(4) Call instruction/branch instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand 1st Operand Basic instruction Compound Instruction BR
AX
!addr16 CALL BR
!addr11 CALLF
[addr5] CALLT
$addr16 BR, BC, BNC, BZ, BNZ BT, BF, BTCLR DBNZ
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
36
Data Sheet U11105EJ3V1DS
PD780306, 780308
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25C)
Parameter Symbol VDD Supply voltage AVREF AVSS Input voltage Output voltage Analog input voltage VI VO VAN P10-P17 1 pin Output current, high IOH Total for P01-P05, P10-P17, P25-P27, P70-P72, P110-P117 Total for P30-P37, P80-P87, P90-P97, P100-P103 Peak value 1 pin r.m.s. value Total for P01-P05, P10-P17, P110-P117 Output current, low IOL Total for P30-P37, P100-P103 Peak value r.m.s. value Peak value r.m.s. value Total for P25-P27, P70-P72, P80-P87, P90-P97
Operating ambient temperature
Test Conditions
Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3
Unit V V V V V V V mA mA mA mA mA mA mA mA mA mA C C
Analog input pin
AVSS - 0.3 to AVREF + 0.3 -10 -15 -15 30 15
Note
60 40
Note
140 100
Note
Peak value r.m.s. value
50 20
Note
TA Tstg
-40 to +85 -65 to +150
Storage temperature
Note
The r.m.s. value should be calculated as follows: [r.m.s. value] = [Peak value] x Duty Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Caution
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
CAPACITANCE (TA= 25 C, VDD = VSS = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz unmeasured pins returned to 0 V. Test Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
Data Sheet U11105EJ3V1DS
37
PD780306, 780308
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.0Note 4 to 5.5 V)
Recommended Circuit
IC R1 C2 C1 X2 X1
Resonator Ceramic resonator
Parameter Oscillator frequency (fX)Note 1 Oscillation stabilization timeNote 2 Oscillator frequency (fX)Note 1 Oscillation stabilization timeNote 2 X1 input frequency (fX)Note 1 X1 input high/low level width (tXH , tXL)
Test Conditions VDD = Oscillator voltage range After VDD reaches oscillator voltage range MIN. VDD = Oscillator voltage range VDD = 4.5 to 5.5 VNote 3 Note 3
MIN.
TYP.
MAX.
Unit
1
5
MHz
4
ms
Crystal resonator
IC R1 C2
X2
X1
1
5 10
MHz
C1
ms 30 1.0 5.0 MHz
External clock
X2
X1
PD74HCU04
85
500
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. 3. After VDD reaches the minimum oscillator voltage range. 4. Actually, oscillation start voltage or over, and VDD = 2.0 or over (For an external clock, VDD = 2.0 or over is OK). Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS1. * Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. 2. If the main system clock oscillator is operated by the subsystem clock when the main system clock is stopped, reswitching to the main system clock should be performed after the stable oscillation time has been obtained by the program.
38
Data Sheet U11105EJ3V1DS
PD780306, 780308
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85C, VDD = 2.0Note 4 to 5.5 V)
Resonator Parameter Oscillator frequency (fXT)Note 1 Test Conditions VDD = Oscillator voltage range VDD = 4.5 to 5.5 VNote 3 Note 3 MIN. TYP. MAX. Unit
Recommended Circuit
IC XT1
Crystal resonator
XT2 R2
32
32.768
35
kHz
C3
C4
Oscillation stabilization timeNote 2
1.2
2 10
s
XT1 External clock
XT2
XT1 input frequency (fXT)Note 1
32
100
kHz
XT1 input high-/low-level width (tXTH/tXTL)
5
15
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD has reached the minimum oscillation voltage range. 3. After VDD reaches the minimum oscillator voltage range. 4. Actually, oscillation start voltage or over, and VDD = 2.0 or over (For an external clock, VDD = 2.0 or over is OK). Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS1. * Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. 2. The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption current, causing misoperation to noise more frequently than the main system clock oscillator. Special care should therefore be taken to wiring method when the subsystem clock is used.
Data Sheet U11105EJ3V1DS
39
PD780306, 780308
RECOMMENDED OSCILLATOR CONSTANT MAIN SYSTEM CLOCK: CERAMIC RESONATOR (TA = -40 to +85 C)
Frequency Manufacturer Matsushita Electronics Components Co., Ltd. Product Name (MHz) EFOEC2004A5 EFOEC3584A4 EFOEC4194A4 EFOEC4914A4 EFOEC5004A4 TDK Corp. CCR1000K2 CCR3.58MC3 CCR4.19MC3 CCR4.91MC3 CCR5.0MC3 Murata Mfg. Co., Ltd. CSB1000J CSA2.00MG040 CST2.00MG040 CSA3.58MG CST3.58MGW CSA4.19MG CST4.19MGW CSA4.91MG CST4.91MGW CSA5.00MG CST5.00MGW 2.00 3.58 4.19 4.91 5.00 1.00 3.58 4.19 4.91 5.00 1.00 2.00 2.00 3.58 3.58 4.19 4.19 4.91 4.91 5.00 5.00 C1 (pF) Built-in Built-in Built-in Built-in Built-in 150 Built-in Built-in Built-in Built-in 100 100 Built-in 30 Built-in 30 Built-in 30 Built-in 30 Built-in C2 (pF) Built-in Built-in Built-in Built-in Built-in 150 Built-in Built-in Built-in Built-in 100 100 Built-in 30 Built-in 30 Built-in 30 Built-in 30 Built-in R1 (k) 4.7 0 0 0 0 0 0 0 0 0 2.2 0 0 0 0 0 0 0 0 0 0 MIN. (V) 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 MAX. (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Recommended Circuit Constant Oscillator Voltage Range
Caution
The oscillator constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used.
40
Data Sheet U11105EJ3V1DS
PD780306, 780308
DC CHARACTERISTICS (TA = -40 to +85C, VDD = 2.0 to 5.5 V)
Parameter
Symbol
Test Conditions P10-P17, P30-P32, VDD = 2.7 to 5.5 V
MIN. 0.7 VDD 0.8 VDD
TYP.
MAX. VDD VDD VDD VDD VDD VDD VDD VDD VDD 0.3 VDD 0.2 VDD 0.2 VDD 0.15 VDD 0.4 0.2 0.2 VDD 0.1 VDD 0.1 VDD VDD VDD
Unit V V V V V V V V V V V V V V V V V V V V V
VIH1
P35-P37, P80-P87, P90-P97, P100-P103 P00-P05, P25-P27, VDD = 2.7 to 5.5 V 0.8 VDD 0.85 VDD VDD = 2.7 to 5.5 V VDD-0.5 VDD-0.2 4.5 VDD 5.5 V 0.8 VDD 0.9 VDD 0.9 VDD 0 0 VDD = 2.7 to 5.5 V 0 0 VDD = 2.7 to 5.5 V 0 0 4.5 VDD 5.5 V 0 0 0 VDD-1.0 VDD-0.5 VDD = 4.5 to 5.5 V, IOL = 15 mA 0.6
VIH2 Input voltage, high
P33, P34, P70-P72, P110-P117, RESET
VIH3
X1, X2
VIH4
XT1/P07, XT2
2.7 VDD < 4.5 V 2.0 VDD < 2.7 VNote
P10-P17, P30-P32, VIL1 P35-P37, P80-P87, P90-P97, P100-P103 P00-P05, P25-P27, VIL2 Input voltage, low VIL3 P33, P34, P70-P72, P110-P117, RESET X1, X2
VDD = 2.7 to 5.5 V
VIL4
XT1/P07, XT2
2.7 VDD < 4.5 V 2.0 VDD < 2.7 VNote
Output voltage, high
VDD = 4.5 to 5.5 V IOH = -1 mA VOH IOH = -100 A P100-P103 VOL1 P01-P05, P25-P27, P70-P72, P90-P97, P10-P17, P30-P37, P80-P87, P110-P117
2.0
Output voltage, low
VDD = 4.5 to 5.5 V, IOL = 1.6 mA
0.4
V
VOL2
SB0, SB1, SCK0 IOL = 400 A
VDD = 4.5 to 5.5 V, open-drain, pulled up (R = 1 k)
0.2 VDD
V
VOL3
0.5
V
Note
When used as P07, the inverse phase of P07 should be input to XT2 using an inverter. Unless specified otherwise, the characteristics of alternate-function pins are the same as the those of port pins.
Remark
Data Sheet U11105EJ3V1DS
41
PD780306, 780308
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.0 to 5.5 V)
Parameter Symbol Test Conditions P00-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 X1, X2, XT1/P07, XT2 P00-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 X1, X2, XT1/P07, XT2 VOUT = VDD VOUT = 0 V P01-P05, P10-P17, P25P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 = = = = = = = = = = = = = = = = = = = = = = 5.0 3.0 2.2 5.0 3.0 5.0 3.0 2.2 5.0 3.0 5.0 3.0 2.2 5.0 3.0 2.2 5.0 3.0 2.2 5.0 3.0 2.2 V V V V V V V V V V V V V V V V V V V V V V 10%Note 5 10%Note 6 10%Note 6 10%Note 5 10%Note 6 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% MIN. TYP. MAX. Unit
Input leakage current, high
ILIH1 VIN = VDD ILIH2 ILIL1 VIN = 0 V ILIH2
3
A
20
A A
Input leakage current, low
-3
-20 3 -3
A A A
Output leakage current, high Output leakage current, low Software pull-up resistor
ILOH ILOL
R
VIN = 0 V
15
45
90
k
IDD1
IDD2
Supply currentNote 1
IDD3
IDD4
IDD5
IDD6
VDD VDD VDD 5.00 MHz, Crystal oscillation (fXX VDD = 5.0 MHz)Note 3 operating mode VDD VDD 5.00 MHz, Crystal oscillation VDD (fXX = 2.5 MHz)Note 2 VDD HALT mode 5.00 MHz, Crystal oscillation (fXX VDD = 5.0 MHz)Note 3 HALT mode VDD VDD 32.768 kHz, Crystal oscillation VDD operating modeNote 4 VDD VDD 32.768 kHz, Crystal oscillation VDD Note 4 HALT mode VDD VDD XT1 = VDD STOP mode VDD When feedback resistor is connected VDD VDD XT1 = VDD STOP mode VDD When feedback resistor is disconnected VDD 5.00 MHz, Crystal oscillation (fXX = 2.5 MHz)Note 2 operating mode
4 0.6 0.35 6.5 0.8 1.4 500 280 1.6 650 60 32 24 25 5 2.5 1 0.5 0.3 0.1 0.05 0.05
12 1.8 1.05 19.5 2.4 4.2 1500 840 4.8 1950 120 64 48 55 15 12.5 30 10 10 30 10 10
mA mA mA mA mA mA A A mA A A A A A A A A A A A A A
Notes 1. Current flowing VDD pin. Not including A/D converter, ports, on-chip pull-up resistors or LCD dividing resistors. 2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 3. Main system clock fXX = fX operation (when OSMS is set to 01H) 4. When the main system clock is stopped. 5. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 6. Low-speed mode operation (when PCC is set to 04H) Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as the those of port pins.
42
Data Sheet U11105EJ3V1DS
PD780306, 780308
LCD CONTROLLER/DRIVER CHARACTERISTICS (AT NORMAL OPERATION) (1) Static Display Mode (TA = -10 to +85 C, VDD = 2.0 to 5.5 V)
Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS IO = 5 A VLCD0 = VLCD IO = 1 A 0 0.2 V Test Conditions MIN. 2.0 60 0 TYP. 100 MAX. VDD 150 0.2 Unit V k V
Note
The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2).
(2) 1/3 Bias Method (TA = -10 to +85 C, VDD = 2.5 to 5.5 V)
Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS IO = 5 A IO = 1 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 Test Conditions MIN. 2.5 60 0 0 TYP. MAX. VDD 150 0.2 0.2 Unit V k V V
100
Note
The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2).
(3) 1/2 Bias Method (TA = -10 to +85 C, VDD = 2.7 to 5.5 V)
Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote(segment) Symbol VLCD RLCD VODC VODS IO = 5 A IO = 1 A VLCD0 = VLCD VLCD1 = VLCD x 1/2 VLCD2 = VLCD1 Test Conditions MIN. 2.7 60 0 0 TYP. MAX. VDD 150 0.2 0.2 Unit V k V V
100
Note
The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2).
Data Sheet U11105EJ3V1DS
43
PD780306, 780308
LCD CONTROLLER/DRIVER CHARACTERISTICS (AT LOW-VOLTAGE OPERATION) (1) Static Display Mode (TA = -10 to +85 C, 2.0 V VDD < 3.4 V)
Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS IO = 5 A VLCD0 = VLCD IO = 1 A 0 0.2 V Test Conditions MIN. 2.0 60 0 TYP. 100 MAX. VDD 150 0.2 Unit V k V
Note
The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2).
(2) 1/3 Bias Method (TA = -10 to +85 C, 2.0 V VDD < 3.4 V)
Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS IO = 5 A IO = 1 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 Test Conditions MIN. 2.0 60 0 0 TYP. MAX. VDD 150 0.2 0.2 Unit V k V V
100
Note
The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2).
(3) 1/2 Bias Method (TA = -10 to +85 C, 2.0 V VDD < 3.4 V)
Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS IO = 5 A IO = 1 A VLCD0 = VLCD VLCD1 = VLCD x 1/2 VLCD2 = VLCD1 Test Conditions MIN. 2.0 60 0 0 TYP. MAX. VDD 150 0.2 0.2 Unit V k V V
100
Note
The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2).
44
Data Sheet U11105EJ3V1DS
PD780306, 780308
AC CHARACTERISTICS (1) Basic Operation (TA = -40 to +85 C, VDD = 2.0 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Symbol TCY Test Conditions Operating on main system clock (fXX = 2.5 MHz)Note 1 Operating on main system clock (fXX = 5.0 MHz)Note 2 Operating on subsystem clock TI00 input frequency TI00 input high/ low-level width fTI00 fTI00 = tTIH00 + tTIL00 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V 2.0 V VDD < 2.7 V TI01 input frequency TI01 input high/ low-level width TI1, TI2 input frequency TI1, TI2 input high/low-level width Interrupt request input high/lowlevel width fTI01 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 3.5 VDD 5.5 V 2.7 VDD < 3.5 V MIN. 0.8 2.0 0.4 0.8 40Note 3 0 122 TYP. MAX. 64 64 32 32 125 1/tTI00 Unit
s s s s s
MHz
tTIH00, tTIL00
2/fsam+0.1Note 4 2/fsam+0.2Note 4 2/fsam+0.5Note 4 0 0 100 50
s s s
kHz kHz
tTIH01, tTIL01 fTI1
VDD = 2.7 to 5.5 V
10 20
s s
4 275 MHz kHz ns
VDD = 4.5 to 5.5 V
0 0
tTIH, tTIL tINTH, tINTH, tINTH, tINTL
VDD = 4.5 to 5.5 V
100 1.8 3.5 V VDD 5.5 V 2/fsam+0.1Note 4 2.7 V VDD < 3.5 V 2.0 V VDD < 2.7 V 2/fsam+0.2Note 4 2/fsam+0.5Note 4 10 20
s s s s s s s s
INTP0
INTP1-INTP5, P110-P117
VDD = 2.7 to 5.5 V
RESET low level width
tRST
VDD = 2.7 to 5.5 V
10 20
Notes 1. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 2. Main system clock fXX = fX operation (when OSMS is set to 01H) 3. This is the value when the external clock is used. The value is 114 s (min.) when the crystal resonator is used. 4. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is possible between fXX/2N, fXX/32, fXX/64 and fXX/128 (when N = 0 to 4).
Data Sheet U11105EJ3V1DS
45
PD780306, 780308
TCY vs VDD (At main system clock fXX = fX/2 operation)
TCY vs VDD (At main system clock fXX = fX operation)
60
60 32
Cycle Time TCY [ s]
10 Guaranteed Operation Range
Cycle Time TCY [ s]
10 Guaranteed Operation Range
2.0
2.0
1.0 0.8 0.4
1.0 0.8 0.4
0
1
2
2.7 3
4
5
6
0
1
2
3 3.5 4
5
6
Supply Voltage VDD [V]
Supply Voltage VDD [V]
46
Data Sheet U11105EJ3V1DS
PD780306, 780308
(2) Serial Interface (TA = -40 to +85 C, VDD = 2.0 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0... Internal clock output)
Symbol Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V VDD = 4.5 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 tKCY1/2-50 tKCY1/2-100 100 150 300 400 C = 100 pFNote 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Parameter
SCK0 cycle time
tKCY1 tKH1, tKL1 tSIK1
SCK0 high/low-level width
SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0
tKSI1 tKSO1
Note C is the load capacitance of SCK0, SO0 output line. (ii) 3-wire serial I/O mode (SCK0...External clock input)
Parameter Symbol Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 400 800 1600 100 400 C = 100 pFNote 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
SCK0 cycle time
tKCY2
SCK0 high/low-level width
tKH2, tKL2 tSIK2 tKSI2 tKSO2 tR2, tF2
SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 rise, fall time
1000
ns
Note C is the load capacitance of SO0 output line.
Data Sheet U11105EJ3V1DS
47
PD780306, 780308
(iii) SBI mode (SCK0...Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 3200 SCK0 high/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKH3, tKL3 tSIK3 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKCY3/2-50 tKCY3/2-150 100 300 tKSI3 tKCY3/2 ns ns ns ns ns ns Test Conditions VDD = 4.5 to 5.5 V MIN. 800 TYP. MAX. Unit ns
tKSO3 tKSB tSBK tSBH
R = 1 k , C = 100 pFNote
VDD = 4.5 to 5.5 V
0 0 tKCY3 tKCY3 tKCY3
250 1000
ns ns ns ns ns
tSBL
tKCY3
ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line. (iv) SBI mode (SCK0...External clock input)
Parameter SCK0 cycle time Symbol tKCY4 3200 SCK0 high/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK0 rise, fall time tKH4, tKL4 tSIK4 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V 400 1600 100 300 tKSI4 tKCY4/2 ns ns ns ns ns ns Test Conditions VDD = 4.5 to 5.5 V MIN. 800 TYP. MAX. Unit ns
tKSO4 tKSB tSBK tSBH
R = 1 k , C = 100 pFNote
VDD = 4.5 to 5.5 V
0 0 tKCY4 tKCY4 tKCY4
300 1000
ns ns ns ns ns
tSBL tR4, tF4
tKCY4 1000
ns ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line. 48
Data Sheet U11105EJ3V1DS
PD780306, 780308
(v) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 Symbol tKCY5 tKH5 tKL5 R = 1 k, C = 100 pFNote Test Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 4.5 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. 1600 3200 tKCY5/2-160 tKCY5/2-190 tKCY5/2-50 tKCY5/2-100 300 350 400 600 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
tSIK5
tKSI5 tKSO5
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line. (vi) 2-wire serial I/O mode (SCK0... External clock input)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SCK0 rise, fall time Symbol tKCY6 tKH6 tKL6 tSIK6 tKSI6 tKSO6 tR6, tF6 R = 1 k, VDD = 4.5 to 5.5 V C = 100 pFNote Test Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V MIN. 1600 3200 650 1300 800 1600 100 tKCY6/2 0 0 300 500 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
Data Sheet U11105EJ3V1DS
49
PD780306, 780308
(b) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2... Internal clock output)
Symbol Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V VDD = 4.5 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 tKCY7/2-50 tKCY7/2-100 100 150 300 400 C = 100 pFNote 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Parameter
SCK2 cycle time
tKCY7 tKH7, tKL7 tSIK7
SCK2 high/low-level width
SI2 setup time (to SCK2) SI2 hold time (from SCK2) SO2 output delay time from SCK2
tKSI7 tKSO1
Note C is the load capacitance of SCK2, SO2 output line. (ii) 3-wire serial I/O mode (SCK2...External clock input)
Parameter Symbol Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 400 800 1600 100 400 C = 100 pFNote 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
SCK2 cycle time
tKCY8
SCK2 high/low-level width
tKH8, tKL8 tSIK8 tKSI8 tKSO8 tR8, tF8
SI2 setup time (to SCK2) SI2 hold time (from SCK2) SO2 output delay time from SCK2 SCK2 rise, fall time
1000
ns
Note C is the load capacitance of SO2 output line.
50
Data Sheet U11105EJ3V1DS
PD780306, 780308
(iii) UART mode (Dedicated baud rate generator output)
Parameter Symbol Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. TYP. MAX. 78125 39063 19531 Unit bps bps bps
Transfer rate
(iv) UART mode (External clock input)
Parameter Symbol Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 400 800 1600 39063 19531 9766 1000 TYP. MAX. Unit ns ns ns ns ns ns bps bps bps ns
ASCK cycle time
tKCY9
ASCK high/low-level width
tKH9, tKL9
Transfer rate
ASCK rise, fall time
tR9, tF9
Data Sheet U11105EJ3V1DS
51
PD780306, 780308
(c) Serial interface channel 3 (i) 3-wire serial I/O mode (SCK3... Internal clock output)
Symbol Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V VDD = 4.5 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 tKCY10/2-50 tKCY10/2-100 100 150 300 400 C = 100 pFNote 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Parameter
SCK3 cycle time
tKCY10 tKH10, tKL10 tSIK10
SCK3 high/low-level width
SI3 setup time (to SCK3) SI3 hold time (from SCK3) SO3 output delay time from SCK3
tKSI10 tKSO10
Note
C is the load capacitance of SCK3, SO3 output line. (ii) 3-wire serial I/O mode (SCK3...External clock input)
Parameter Symbol Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. 800 1600 3200 400 800 1600 100 400 C = 100 pFNote 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
SCK3 cycle time
tKCY11
SCK3 high/low-level width
tKH11, tKL11 tSIK11 tKSI11 tKSO11 tR11, tF11
SI3 setup time (to SCK3) SI3 hold time (from SCK3) SO3 output delay time from SCK3 SCK3 rise, fall time
1000
ns
Note
C is the load capacitance of SO3 output line.
52
Data Sheet U11105EJ3V1DS
PD780306, 780308
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
Clock Timing
1/fX
tXL
tXH VIH3 (MIN.) VIL3 (MAX.)
X1 Input
1/fXT
tXTL XT1 Input
tXTH VIH4 (MIN.) VIL4 (MAX.)
TI Timing
1/fTI00, 01 tTIL00, tTIL01 tTIH00, tTIH01
TI00, TI01
1/fTI1
tTIL1
tTIH1
TI1, TI2
Data Sheet U11105EJ3V1DS
53
PD780306, 780308
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm
tKLm tRn SCK0, SCK2, SCK3 tSIKm tKSIm
tKHm tFn
SI0, SI2, SI3 tKSOm
Input data
SO0, SO2, SO3
Output data
m = 1, 2, 7, 8, 10, 11 n = 2, 8, 11
SBI mode (bus release signal transfer):
tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 tF4
SB0, SB1 tKSO3, 4
SBI mode (command signal transfer):
tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBK tSIK3, 4 tKSI3.4 tKH3, 4 tF4
SB0, SB1 tKSO3, 4
54
Data Sheet U11105EJ3V1DS
PD780306, 780308
2-wire serial I/O mode:
tKCY5.6 tKL5, 6 tR6 SCK0 tSIK5, 6 tKSO5, 6 SB0, SB1 tKSI5, 6 tKH5, 6 tF6
UART mode:
tKCY9 tKL9 tR9 ASCK tKH9 tF9
A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 1 2.7 V AVREF 5.5 2.0 V AVREF < 2.7 V Conversion time Sampling time Analog input voltage Reference voltage AVREF-AVSS resistance AVREF current tCONV tSAMP VIAN AVREF RREF AIREF When not operating A/D conversion When operating A/D conversionNote 2 When not operating A/D conversionNote 3 19.1 12/fXX AVSS 2.0 4 14 2.5 0.5 5.0 1.5 AVREF AVDD Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 0.6 1.4 200 Unit bit % %
s s
V V k mA mA
Notes 1. Quantization error (1/2 LSB) is not included. This is expressed in proportion to the full-scale value. 2. Indicates current flowing to AVREF pin when the CS bit of the A/D converter mode register (ADM) is 1. 3. Indicates current flowing to AVREF pin when the CS bit of the ADM is 0.
Data Sheet U11105EJ3V1DS
55
PD780306, 780308
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = -40 to +85 C)
Parameter Data retention supply voltage Data retention power supply current Symbol VDDDR VDDDR = 1.6 V Subsystem clock stop and feed-back resistor disconnected 0 Release by RESET tWAIT Release by interrupt Note ms 217/fX Test Conditions MIN. 1.6 TYP. MAX. 5.5 Unit V
IDDDR
0.1
10
A s
ms
Release signal set time Oscillation stabilization wait time
tSREL
Note
In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS), selection of 212/fXX and 214/fXX to 217/fXX is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retention Mode
VDD STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
VDD STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
56
Data Sheet U11105EJ3V1DS
PD780306, 780308
Interrupt Request Input Timing
tINTL
tINTH
INTP0-INTP5
RESET Input Timing
tRSL
RESET
Data Sheet U11105EJ3V1DS
57
PD780306, 780308
11. CHARACTERISTIC CURVES (REFERENCE VALUE)
IDD vs VDD (fX = fXX = 5.0 MHz) 10.0 PCC = 00H (TA = 25 C)
5.0 PCC = 01H PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 oscillation, XT1 oscillation) 1.0
0.5
Supply Current IDD (mA)
0.1
0.05
0.01
0.005
0.001 0 2 3 4 5 6 7 8 Supply Voltage VDD (V)
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Data Sheet U11105EJ3V1DS
PD780306, 780308
IDD vs VDD (fX = 5.0 MHz, fXX = 2.5 MHz) (TA = 25 C)
10.0
5.0 PCC = 00H
PCC = 01H PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 oscillation, XT1 oscillation) 1.0
0.5
Supply Current IDD (mA)
0.1
PCC = B0H 0.05 HALT (X1 stopped, XT1 oscillation)
0.01
0.005
0.001 0 2 3 4 5 6 7 8 Supply Voltage VDD (V)
Data Sheet U11105EJ3V1DS
59
PD780306, 780308
12. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P H I
M
J K S
N
S L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 +7 3 -3 1.60 MAX.
S100GC-50-8EU, 8EA-2
Remark
Dimensions and materials of ES products are the same as those of the mass production product.
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Data Sheet U11105EJ3V1DS
PD780306, 780308
100-PIN PLASTIC QFP (14x20)
A B
80 81
51 50
detail of lead end S CD Q R
100 1
31 30
F G H I
M
J
P
K S N S L M
NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15+0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX.
P100GF-65-3BA1-4
Remark
Dimensions and materials of ES products are the same as those of the mass production product.
Data Sheet U11105EJ3V1DS
61
PD780306, 780308
13. RECOMMENDED SOLDERING CONDITIONS
The PD780306 and 780308 should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our sales personnel. Table 13-1. Surface Mounting Type Soldering Conditions (1) PD780306GF-xxx-3BA: 100-pin plastic QFP (14 x 20 mm)
PD780308GF-xxx-3BA: 100-pin plastic QFP (14 x 20 mm)
Recommended Soldering Symbols IR35-00-3 VP15-00-3 WS60-00-1 --
Soldering Method Infrared reflow VPS Wave soldering Partial heating
Soldering Conditions Package peak temperature: 235 C, Duration: 30 sec. max. (at 210 C or above), Number of times: Three times max. Package peak temperature: 215 C, Duration: 40 sec. (at 200 C or above), Number of times: Three times max. Solder bath temperature: 260 C max., Duration: 10 sec. max., Number of times: Once, Preheating temperature: 120 C max. (Package surface temperature) Pin temperature: 300 C max., Duration: 3 sec. max. (per device side)
(2) PD780306GC-xxx-8EU: 100-pin plastic LQFP (fine pitch)(14 x 14 mm)
PD780308GC-xxx-8EU: 100-pin plastic LQFP (fine pitch)(14 x 14 mm)
Recommended Soldering Symbols IR35-00-2 VP15-00-2 --
Soldering Method Infrared reflow VPS Partial heating
Soldering Conditions Package peak temperature: 235 C, Duration: 30 sec. max. (at 210 C or above), Number of times: Twice max. Package peak temperature: 215 C, Duration: 40 sec. (at 200 C or above), Number of times: Twice max. Pin temperature: 300 C max., Duration: 3 sec. max. (per device side)
Caution
Use of more than one soldering method should be avoided (except in the case of partial heating).
62
Data Sheet U11105EJ3V1DS
PD780306, 780308
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using PD780306/780308. Also refer to (5) Notes on using development tools. (1) Language Processing Software
RA78K0 CC78K0 DF780308 CC78K0-L 78K/0 series common assembler package 78K/0 series common C compiler package
PD780308 subseries device file (Part number : SxxxxDF78064)
78K/0 series common C compiler library source file
(2) PROM Writing Tools
PG-1500 PA-78P0308GC-8EU PA-78P0308GF PA-78P0308KL-T PG-1500 controller PG-1500 control program PROM programmer
Programmer adapters connected to PG-1500
(3) Debugging Tools * When in-circuit emulator IE-78K0-NS is used
IE-78K0-NS IE-70000-MC-PS-B IE-78K0-NS-PA IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-780308-NS-EM1 NP-100GC NP-100GF TGC-100SDW In-circuit emulator common to 78K/0 series Power supply unit for IE-78K0-NS Performance board to enhance/expand functions of IE-78K0-NS Adapter when using PC-9800 series as host machine (excluding notebook type PCs) (C bus supported) PC card and interface cable when using notebook type PC as host machine (PCMCIA socket supported) Adapter when using IBM PC/ATTM compatible as host machine (ISA bus supported) Interface adapter required when using PC with on-chip PCI bus as host machine Emulation board to emulate PD780308 subseries Emulation probe for 100-pin plastic LQFP (GC-3EU type) Emulation probe for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect NP-100GC and a target system board made to be mounted on 100-pin plastic LQFP (GC-8EU type) Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) Integrated debugger for IE-78K0-NS 78K/0 series common system simulator
EV-9200GF-100 ID78K0-NS SM78K0 DF780308
PD780308 subseries device file (Part number: SxxxxDF78064)
Data Sheet U11105EJ3V1DS
63
PD780306, 780308
* When in-circuit emulator IE-78001-R-A is used
IE-78001-R-A IE-70000-98-IF-C In-circuit emulator common to 78K/0 series Adapter required when PC-9800 series (except notebook type) is used as host machine (C bus supported) Adapter required when IBM PC/AT compatible machine is used as host machine (ISA bus supported) Interface adapter required when using PC with on-chip PCI bus as host machine Interface adapter and cable required when EWS is used as host machine Emulation board to emulate PD780308 subseries
IE-70000-PC-IF-C
IE-70000-PCI-IF-A IE-78000-R-SV3 IE-780308-NS-EM1 IE-780308-R-EM IE-78K0-R-EX1 NP-100GC NP-100GF TGC-100SDW
Emulation probe conversion board necessary when using IE-780308-NS-EM1 on IE-78001-R-A Emulation probe for 100-pin plastic LQFP (GC-8EU type) Emulation probe for 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect NP-100GC and a target system board made to be mounted on 100-pin plastic LQFP (GC-8EU type) Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type) Integrated debugger for IE-78001-R-A System simulator common to 78K/0 series Device file for PD780308 subseries (Part number: SxxxxDF78064)
EV-9200GF-100 ID78K0 SM78K0 DF780308
(4) Real-Time OS
RX78K0 MX78K0 78K/0 series real-time OS 78K/0 series OS
64
Data Sheet U11105EJ3V1DS
PD780306, 780308
(5) Notes on using development tools * The package name of DF780308 is the DF78064. * Use ID78K0-NS, ID78K0, and SM78K0 in combination with DF780308. * Use CC78K0 and RX78K0 in combination with RA78K0 and DF780308. * NP-100GC and NP-100GF are products of Naito Densei Machida Mfg. Co., Ltd. (TEL (044) 822-3813). * TGC-100SDW is a product of TOKYO ELETECH CORPORATION. Contact: Daimaru Kogyo Ltd. Tokyo Electronics Department (TEL: +81-3-3820-7112) Osaka Electronics Department (TEL: +81-6-6244-6672) * For third party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide (U11069E). * The host machines and OS suitable for each each software are as follows.
Host Machine [OS] Software RA78K0 CC78K0 PG-1500 controller ID78K0-NS ID78K0 SM78K0 RX78K0 MX78K0 PC PC-9800 series [Japanese Windows TM] IBM PC/AT Compatible Machines [Japanese/English Windows] Note Note
Note
EWS HP9000 series 700TM [HP-UX TM] SPARCstation TM [SunOS TM, Solaris TM] -- -- --

Note
Note
Note
This software is based on DOS.
Data Sheet U11105EJ3V1DS
65
PD780306, 780308
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are nor marked as such.
Documents Related to Devices
Document Name Document No. U11377E This document U12251E U11776E U11832E U12326E Basic (III) U10182E
PD780308, 780308Y Subseries User's Manual PD780306, 780308 Data Sheet PD780306Y, 780308Y Data Sheet PD78P0308 Data Sheet PD78P0308Y Data Sheet
78K/0 Series User's Manual (Instruction) 78K/0 Series Application Note
Documents Related to Development Tools (User's Manual)
Document Name RA78K0 Assembler Package Operation Language Structured assembly language CC78K0 C Compiler Operation Language PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOSTM) Based PG-1500 Controller IBM PC Series (PC DOSTM) Based IE-78K0-NS IE-78K0-NS-A IE-78001-R-A IE-780308-NS-EM1 IE-780308-R-EM EP-78064 SM78K0S, SM78K0 System Simulator Ver.2.10 or Later Windows Based SM78K Series System Simulator Ver. 2.10 or Later ID78K0-NS Integrated Debugger Ver 2.00 or Later Windows Based ID78K0 Integrated Debugger Windows Based External Part User Open Interface Specifications Operation Reference Guide U15006E U14379E U11539E U11649E Operation Document No. U14445E U14446E U11789E U14297E U14298E U11940E EEU-1291 U10540E U13731E U14889E Planned U13304E U11362E EEU-1469 U14611E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
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Data Sheet U11105EJ3V1DS
PD780306, 780308
Documents Related to Embedded Software (User's Manuals)
Document Name 78K/0 Series Real-Time OS Fundamentals Installation 78K/0 Series OS MX78K0 Fundamental Document No. U11537E U11536E U12257E
Other Documents
Document Name SEMICONDUCTOR SELECTION GUIDE-Products & Packages- (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769E C10535E C11531E C10983E C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U11105EJ3V1DS
67
PD780306, 780308
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
FIP and IEBus are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS and Solaris are trademarks of Sun Microsystems, Inc.
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Data Sheet U11105EJ3V1DS
PD780306, 780308
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Data Sheet U11105EJ3V1DS
69
PD780306, 780308
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is current as of March, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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